lowRISC/ibex

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

2026 stars · 793 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Ibex is a production-quality, open-source 32-bit RISC-V CPU core written in SystemVerilog, originally developed as 'Zero-riscy' in the PULP platform and now maintained by lowRISC. It is heavily parametrizable, extensively verified, supports RV32I/E/M/C/B extensions, and has seen multiple tape-outs including use in OpenTitan.

Use cases

• embed a small RISC-V CPU core in a custom SoC or FPGA design
• find a verified open-source RV32IMC processor for embedded control applications
• build a secure microcontroller around an open-source CPU core
• compare area and CoreMark performance of configurable RISC-V cores
• integrate a CPU core into an OpenTitan root-of-trust design
• learn how a production RISC-V pipeline is implemented in SystemVerilog

When to choose

• you need a small, well-verified 32-bit RISC-V core for embedded control or security applications
• you want a parametrizable core with configurable performance, area, and security features like PMP
• you are building on OpenTitan or other lowRISC silicon projects
• you need a permissively licensed (Apache-2.0) CPU core with multiple tape-outs

When to avoid

• you need a high-performance application processor with out-of-order execution or Linux-class features
• you need a 64-bit RISC-V core
• you are not equipped to work with RTL/SystemVerilog and hardware verification flows
• you need a soft core with extensive software ecosystem support out of the box

Facets

library · maturity active

embedded security simulation testing embedded-systems hardware security developer-tools embedded iot risc-v cpu-core systemverilog rtl fpga soc open-source-silicon hardware-design opentitan gpu

Member repositories

For agents

markdown · JSON · MCP: product_card(name="lowRISC/ibex")