# lowRISC/ibex

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Repository: https://github.com/lowRISC/ibex
Canonical: https://ross.abutalabs.com/products/ibex
Homepage: https://www.lowrisc.org
Language: SystemVerilog
License: Apache-2.0
License Family: permissive
Topics: hardware, cpucore, risc-v, rv32, lowrisc, lowrisc-ibex
Last push: 2026-08-20T21:41:31+00:00

## Health v2 (maintenance only)
Score: 76/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 98, release rhythm 35, longevity 100
- inputs: {"age_days": 3312, "days_push": 13, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2026, forks 793 (observed 2026-08-28T04:06:06.825127+00:00)

## What it is
Ibex is a production-quality, open-source 32-bit RISC-V CPU core written in SystemVerilog, originally developed as 'Zero-riscy' in the PULP platform and now maintained by lowRISC. It is heavily parametrizable, extensively verified, supports RV32I/E/M/C/B extensions, and has seen multiple tape-outs including use in OpenTitan.

## Use cases
- embed a small RISC-V CPU core in a custom SoC or FPGA design
- find a verified open-source RV32IMC processor for embedded control applications
- build a secure microcontroller around an open-source CPU core
- compare area and CoreMark performance of configurable RISC-V cores
- integrate a CPU core into an OpenTitan root-of-trust design
- learn how a production RISC-V pipeline is implemented in SystemVerilog

## When to choose
- you need a small, well-verified 32-bit RISC-V core for embedded control or security applications
- you want a parametrizable core with configurable performance, area, and security features like PMP
- you are building on OpenTitan or other lowRISC silicon projects
- you need a permissively licensed (Apache-2.0) CPU core with multiple tape-outs

## When to avoid
- you need a high-performance application processor with out-of-order execution or Linux-class features
- you need a 64-bit RISC-V core
- you are not equipped to work with RTL/SystemVerilog and hardware verification flows
- you need a soft core with extensive software ecosystem support out of the box

## Facets
- artifact type: library
- maturity: active
- function: embedded, security, simulation, testing
- domain: embedded-systems, hardware, security, developer-tools
- platform: embedded, iot
- tags: risc-v, cpu-core, systemverilog, rtl, fpga, soc, open-source-silicon, hardware-design, opentitan, gpu

## Member repositories
- lowRISC/ibex (main) score 76

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:06.825127+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:59:44.284128+00:00, confidence not recorded.
  - readme: https://github.com/lowRISC/ibex (fetched 2026-08-28T04:06:06.825127+00:00, sha f7c650aa832a)
  - homepage: https://www.lowrisc.org (fetched 2026-08-29T10:39:47.692549+00:00, sha 7138d68e5330)
  - site_page: https://lowrisc.org/faqs (fetched 2026-08-29T10:39:47.701701+00:00, sha 9e6772fc49ce)
- Data as of 2026-08-30T08:39:29.467469+00:00.