Wren6991/Hazard3

Health v2 · maintenance only

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1117 stars · 96 forks observed · 2026-10-03

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Hazard3 is a 3-stage RISC-V (RV32IMACZb*) soft processor core written in Verilog, with JTAG/APB debug support, PMP, and hardware breakpoints. It includes a Verilator-based simulator and an example SoC integration for FPGA or ASIC use.

Use cases

• embed a RISC-V CPU core in an FPGA design
• tape out a custom ASIC with an open-source processor
• simulate RISC-V binaries before hardware is available
• add JTAG debugging to a custom SoC
• learn how a pipelined RISC-V core is implemented in Verilog

When to choose

• you need a small, configurable RV32 core with debug support for FPGA or ASIC
• you want an Apache-2.0 licensed processor with a stable release branch for tapeouts
• you need bit-manipulation and crypto-oriented extensions (Zbkb, Zbkx) in a soft core

When to avoid

• you need a 64-bit or out-of-order high-performance processor
• you want an application-class Linux-capable core with MMU
• you prefer not to work with Verilog or FPGA/ASIC toolchains

Facets

library · maturity active

embedded simulation developer-tools hardware embedded-systems developer-tools embedded windows cpp risc-v verilog processor-core jtag-debug fpga asic soc open-hardware linux

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