SI-RISCV/e200_opensource

Health v2 · maintenance only

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2851 stars · 1047 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

The open-source Hummingbird E203 RISC-V processor core and demo SoC, a two-stage pipeline ultra-low power/area CPU implementation written in Verilog by Nuclei System Technology. This repository is deprecated in favor of the next-generation Hummingbirdv2 E203 at riscv-mcu/e203_hbirdv2.

Use cases

• study how a RISC-V CPU core is implemented in Verilog
• university lab practice for processor design courses
• run RISC-V core and SoC on an FPGA for embedded demos
• build custom hardware co-units with a simple RISC-V core
• entry-level learning project for CPU microarchitecture

When to choose

• you need a simple, well-documented ultra-low-power RISC-V core for research or teaching
• you want a complete core-plus-SoC example with docs, software, and FPGA demos
• you are a student or beginner learning RISC-V implementation

When to avoid

• you need a maintained project - use riscv-mcu/e203_hbirdv2 instead
• you require commercial-grade, bug-free silicon-quality IP with support
• you need a high-performance or out-of-order RISC-V core

Facets

library · maturity abandoned

embedded simulation developer-tools embedded-systems hardware education embedded risc-v verilog cpu-core soc iot fpga deprecated nuclei hummingbird-e203

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