# SI-RISCV/e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Repository: https://github.com/SI-RISCV/e200_opensource
Canonical: https://ross.abutalabs.com/products/e200_opensource
Homepage: https://github.com/riscv-mcu/e203_hbirdv2
Language: Verilog
License: Apache-2.0
License Family: permissive
Topics: risc-v, ultra-low-power, cpu, core, china, verilog, nuclei
Archived: true
Last push: 2021-03-24T09:38:39+00:00

## Health v2 (maintenance only)
Score: 10/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 3324, "days_push": 1988, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, archived
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2851, forks 1047 (observed 2026-08-28T04:07:25.675480+00:00)

## What it is
The open-source Hummingbird E203 RISC-V processor core and demo SoC, a two-stage pipeline ultra-low power/area CPU implementation written in Verilog by Nuclei System Technology. This repository is deprecated in favor of the next-generation Hummingbirdv2 E203 at riscv-mcu/e203_hbirdv2.

## Use cases
- study how a RISC-V CPU core is implemented in Verilog
- university lab practice for processor design courses
- run RISC-V core and SoC on an FPGA for embedded demos
- build custom hardware co-units with a simple RISC-V core
- entry-level learning project for CPU microarchitecture

## When to choose
- you need a simple, well-documented ultra-low-power RISC-V core for research or teaching
- you want a complete core-plus-SoC example with docs, software, and FPGA demos
- you are a student or beginner learning RISC-V implementation

## When to avoid
- you need a maintained project - use riscv-mcu/e203_hbirdv2 instead
- you require commercial-grade, bug-free silicon-quality IP with support
- you need a high-performance or out-of-order RISC-V core

## Facets
- artifact type: library
- maturity: abandoned
- function: embedded, simulation, developer-tools
- domain: embedded-systems, hardware, education
- platform: embedded
- tags: risc-v, verilog, cpu-core, soc, iot, fpga, deprecated, nuclei, hummingbird-e203

## Member repositories
- SI-RISCV/e200_opensource (main) score 10

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:25.675480+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:48:31.324693+00:00, confidence not recorded.
  - readme: https://github.com/SI-RISCV/e200_opensource (fetched 2026-08-28T04:07:25.675480+00:00, sha 399c1895762a)
  - homepage: https://github.com/riscv-mcu/e203_hbirdv2 (fetched 2026-08-29T09:52:28.030012+00:00, sha 4d4082b59f33)
- Data as of 2026-08-30T08:39:29.467469+00:00.