chipsalliance/chisel

Health v2 · maintenance only

Adoption not part of the score

4763 stars · 657 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

Chisel is an open-source hardware description language (HDL) embedded in Scala for describing digital electronics at the register-transfer level. It enables parameterizable circuit generators that emit synthesizable Verilog, backed by the FIRRTL compiler framework implemented in LLVM CIRCT.

Use cases

• generate synthesizable Verilog for ASIC designs
• design FPGA digital logic with a modern programming language
• write parameterizable and reusable hardware circuit generators
• build reusable hardware component libraries like FIFOs and arbiters
• verify and test hardware designs with Chisel testing infrastructure
• raise abstraction level over Verilog/VHDL for chip design

When to choose

• you want type-safe, software-engineering-grade abstractions for hardware design
• you need to generate many variants of a circuit programmatically
• you are designing ASIC or FPGA logic and prefer Scala's expressiveness
• you want an actively maintained, CHIPS Alliance-backed open-source HDL

When to avoid

• your team only knows Verilog/VHDL and cannot invest in learning Scala
• you need direct low-level control over Verilog output without a compiler layer
• your toolchain cannot run on the JVM or integrate with Scala build tools
• you are working with analog or mixed-signal design, which Chisel does not target

Facets

library · maturity stable

compiler programming-language simulation testing hardware embedded-systems programming-languages compilers developer-tools jvm windows cross-platform hdl rtl verilog fpga asic firrtl scala hardware-design circuit-generation chipsalliance linux macos

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