# chipsalliance/chisel

Chisel: A Modern Hardware Design Language

Repository: https://github.com/chipsalliance/chisel
Canonical: https://ross.abutalabs.com/products/chipsalliance-chisel
Homepage: https://www.chisel-lang.org/
Language: Scala
License: Apache-2.0
License Family: permissive
Topics: chisel, chisel3, scala, firrtl, rtl, chip-generator, verilog
Last push: 2026-08-23T11:10:44+00:00

## Health v2 (maintenance only)
Score: 98/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 97, longevity 100
- inputs: {"age_days": 4146, "days_push": 10, "days_rel": 20, "gap_med": 21, "n_releases_24m": 18}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 4763, forks 657 (observed 2026-08-28T04:08:59.106977+00:00)

## What it is
Chisel is an open-source hardware description language (HDL) embedded in Scala for describing digital electronics at the register-transfer level. It enables parameterizable circuit generators that emit synthesizable Verilog, backed by the FIRRTL compiler framework implemented in LLVM CIRCT.

## Use cases
- generate synthesizable Verilog for ASIC designs
- design FPGA digital logic with a modern programming language
- write parameterizable and reusable hardware circuit generators
- build reusable hardware component libraries like FIFOs and arbiters
- verify and test hardware designs with Chisel testing infrastructure
- raise abstraction level over Verilog/VHDL for chip design

## When to choose
- you want type-safe, software-engineering-grade abstractions for hardware design
- you need to generate many variants of a circuit programmatically
- you are designing ASIC or FPGA logic and prefer Scala's expressiveness
- you want an actively maintained, CHIPS Alliance-backed open-source HDL

## When to avoid
- your team only knows Verilog/VHDL and cannot invest in learning Scala
- you need direct low-level control over Verilog output without a compiler layer
- your toolchain cannot run on the JVM or integrate with Scala build tools
- you are working with analog or mixed-signal design, which Chisel does not target

## Facets
- artifact type: library
- maturity: stable
- function: compiler, programming-language, simulation, testing
- domain: hardware, embedded-systems, programming-languages, compilers, developer-tools
- platform: jvm, windows, cross-platform
- tags: hdl, rtl, verilog, fpga, asic, firrtl, scala, hardware-design, circuit-generation, chipsalliance, linux, macos

## Member repositories
- chipsalliance/chisel (main) score 98

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:59.106977+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:18:51.041847+00:00, confidence not recorded.
  - readme: https://github.com/chipsalliance/chisel (fetched 2026-08-28T04:08:59.106977+00:00, sha 77c5e8b5c39b)
  - homepage: https://www.chisel-lang.org/ (fetched 2026-08-29T09:02:12.776214+00:00, sha cd12cb28b523)
  - site_page: https://www.chisel-lang.org/docs (fetched 2026-08-29T09:02:12.779411+00:00, sha 97da6130c1df)
  - site_page: https://www.chisel-lang.org/docs/installation (fetched 2026-08-29T09:02:12.781594+00:00, sha 14908466345a)
- Data as of 2026-08-30T08:39:29.467469+00:00.