drom/awesome-hdl resource
Hardware Description Languages observed · 2026-08-28
Health v2 · maintenance only
73/100
- Activity 91
- Release rhythm 35
- Longevity 100
Flags: no_releases no_license
How is this computed?
round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-09-03. Adoption (stars, forks) is never an input.
- gap_med: n/a
- age_days: 3430
- days_rel: n/a
- days_push: 56
- n_releases_24m: 0
Adoption not part of the score
1169 stars · 112 forks observed · 2026-08-28
What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded
A curated awesome-list of hardware description language (HDL) projects, covering Verilog, VHDL, SystemVerilog, Chisel, and other HDLs. It links to standards documents, simulators, compilers, synthesis tools, and HDL libraries.
Use cases
- find a Verilog simulator
- discover VHDL compiler and simulator tools
- learn hardware description language standards
- find HDL libraries for FPGAs
- explore functional HDLs like Clash and Bluespec
- find RTL synthesis tools like Yosys
When to choose
- you are starting with FPGA or ASIC development and need an overview of the HDL ecosystem
- you want a curated index of HDL tools, simulators, and libraries
When to avoid
- you need an actual HDL tool rather than a list of links
- you need detailed tutorials rather than a curated link collection
Facets
learning-resource · maturity active
documentation developer-tools hardware awesome-lists developer-tools cross-platform awesome-list hdl verilog vhdl fpga hardware-description-languages curated-list
1 source
- readme: https://github.com/drom/awesome-hdl · fetched 2026-08-28 · 7bf6cc0c35c0
Member repositories
| Repository | Role | Health v2 |
|---|---|---|
| drom/awesome-hdl | main | 73 |
For agents
markdown · JSON · MCP: product_card(name="drom/awesome-hdl")
Data as of 2026-08-30T08:39:29.467469+00:00 · Report a problem