amaranth-lang/amaranth

Health v2 · maintenance only

Adoption not part of the score

2074 stars · 203 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Amaranth is a Python-based hardware definition language and toolchain for designing synchronous digital logic, including a standard library, simulator, and build system. It targets FPGAs and ASIC flows that accept Verilog-2001, with extended support for Lattice, AMD/Xilinx, Altera, and Quicklogic devices.

Use cases

• design FPGA circuits in Python instead of Verilog
• simulate digital hardware before synthesis
• generate Verilog from a Python hardware description
• build reusable hardware components for FPGA projects
• integrate existing Verilog/VHDL code into a Python-based design flow
• target multiple FPGA vendors with one HDL codebase

When to choose

• you prefer Python syntax and tooling over traditional HDLs
• you need a FOSS FPGA flow with Yosys and nextpnr
• you want simulation, build system, and language in one toolchain
• you need to support multiple FPGA families from a single codebase

When to avoid

• your team is committed to SystemVerilog or VHDL workflows
• you need analog or asynchronous-only design support
• you require vendor-specific tooling not covered by Amaranth's platform integrations

Facets

library · maturity active

programming-language compiler simulation build-tool embedded hardware embedded-systems developer-tools programming-languages python cross-platform fpga hdl digital-logic-design verilog asic hardware-description-language yosys nextpnr

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