# amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

Repository: https://github.com/amaranth-lang/amaranth
Canonical: https://ross.abutalabs.com/products/amaranth
Homepage: https://amaranth-lang.org/docs/amaranth/
Language: Python
License: BSD-2-Clause
License Family: permissive
Topics: fpga, hdl, amaranth-hdl
Last push: 2026-08-23T22:27:47+00:00

## Health v2 (maintenance only)
Score: 93/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 81, longevity 100
- inputs: {"age_days": 2410, "days_push": 10, "days_rel": 48, "gap_med": 64, "n_releases_24m": 8}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2074, forks 203 (observed 2026-08-28T04:06:10.672422+00:00)

## What it is
Amaranth is a Python-based hardware definition language and toolchain for designing synchronous digital logic, including a standard library, simulator, and build system. It targets FPGAs and ASIC flows that accept Verilog-2001, with extended support for Lattice, AMD/Xilinx, Altera, and Quicklogic devices.

## Use cases
- design FPGA circuits in Python instead of Verilog
- simulate digital hardware before synthesis
- generate Verilog from a Python hardware description
- build reusable hardware components for FPGA projects
- integrate existing Verilog/VHDL code into a Python-based design flow
- target multiple FPGA vendors with one HDL codebase

## When to choose
- you prefer Python syntax and tooling over traditional HDLs
- you need a FOSS FPGA flow with Yosys and nextpnr
- you want simulation, build system, and language in one toolchain
- you need to support multiple FPGA families from a single codebase

## When to avoid
- your team is committed to SystemVerilog or VHDL workflows
- you need analog or asynchronous-only design support
- you require vendor-specific tooling not covered by Amaranth's platform integrations

## Facets
- artifact type: library
- maturity: active
- function: programming-language, compiler, simulation, build-tool, embedded
- domain: hardware, embedded-systems, developer-tools, programming-languages
- platform: python, cross-platform
- tags: fpga, hdl, digital-logic-design, verilog, asic, hardware-description-language, yosys, nextpnr

## Member repositories
- amaranth-lang/amaranth (main) score 93

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:10.672422+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:56:22.237214+00:00, confidence not recorded.
  - readme: https://github.com/amaranth-lang/amaranth (fetched 2026-08-28T04:06:10.672422+00:00, sha 5655debbe6e5)
  - homepage: https://amaranth-lang.org/docs/amaranth/ (fetched 2026-08-29T10:36:37.720860+00:00, sha 13d04ca15538)
  - site_page: https://amaranth-lang.org/docs/amaranth/latest (fetched 2026-08-29T10:36:37.730068+00:00, sha 8a8ea05bbd12)
  - registry_pypi: https://pypi.org/pypi/amaranth/json (fetched 2026-08-29T10:36:37.732164+00:00, sha 0bd967c47cf6)
- Data as of 2026-08-30T08:39:29.467469+00:00.