berkeley-abc/abc

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

1216 stars · 785 forks observed · 2026-09-03

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

ABC is a system for sequential logic synthesis and formal verification of digital circuits, developed at UC Berkeley. It can be used as a standalone executable or embedded as a static library, operating on AIGER and BLIF logic networks.

Use cases

• synthesize and optimize sequential logic circuits
• verify equivalence of logic networks
• perform DAG-aware AIG rewriting
• embed logic synthesis into a custom EDA tool via a C library
• model check hardware designs
• convert and process AIGER and BLIF circuit files

When to choose

• you need academic-grade logic synthesis or circuit optimization
• you want formal equivalence checking or model checking for hardware designs
• you need a programmable synthesis engine to embed in your own EDA tooling

When to avoid

• you need a GUI-based circuit design tool
• you are doing high-level synthesis from C/C++ rather than logic-level optimization
• you need commercial-grade support and documentation

Facets

application · maturity active

compiler developer-tools simulation testing hardware developer-tools windows cpp c logic-synthesis formal-verification eda aig model-checking circuit-optimization algorithms research linux macos

Member repositories

For agents

markdown · JSON · MCP: product_card(name="berkeley-abc/abc")