# hughperkins/VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Repository: https://github.com/hughperkins/VeriGPU
Canonical: https://ross.abutalabs.com/products/verigpu
Language: SystemVerilog
License: MIT
License Family: permissive
Topics: verilog, risc-v, risc-v-assembly, hardware-designs, asic-design, gpu, gpu-acceleration, machine-learning, verification
Last push: 2024-11-22T04:42:11+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 1646, "days_push": 649, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1364, forks 144 (observed 2026-08-28T04:04:31.057894+00:00)

## What it is
VeriGPU is an open-source GPU written in SystemVerilog, loosely based on the RISC-V ISA and targeting eventual ASIC tape-out for machine learning workloads. It includes a GPU runtime, single-source C++ compilation flow, and simulation tooling, with the goal of being compatible with PyTorch via a HIP-like API.

## Use cases
- build an open-source GPU in Verilog for machine learning
- simulate a RISC-V-based GPU core before ASIC tape-out
- run PyTorch workloads on a custom open-source GPU
- learn GPU architecture and hardware design in SystemVerilog
- experiment with BF16-focused ML accelerator cores
- verify timing and correctness of a custom GPU design

## When to choose
- you want to study or modify an open-source GPU hardware design written in SystemVerilog
- you need a simulated RISC-V-like GPU core for ML experiments
- you are exploring ASIC tape-out of a custom ML accelerator
- you want a PyTorch-compatible open hardware GPU project to contribute to

## When to avoid
- you need a production GPU with mature drivers and real hardware performance today
- you want a drop-in replacement for NVIDIA or AMD GPUs in a training pipeline
- you need CUDA or SYCL support that is fully implemented and stable
- you are not prepared to work with hardware description languages and simulation tooling

## Facets
- artifact type: library
- maturity: experimental
- function: gpu-computing, machine-learning, simulation, compiler, sdk
- domain: hardware, gpu-computing, machine-learning, embedded-systems
- platform: cpp, python
- tags: verilog, systemverilog, risc-v, asic-design, open-source-gpu, pytorch, hip, hardware-verification, bfloat16, linux

## Member repositories
- hughperkins/VeriGPU (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:31.057894+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:41:21.165565+00:00, confidence not recorded.
  - readme: https://github.com/hughperkins/VeriGPU (fetched 2026-08-28T04:04:31.057894+00:00, sha ee679007b6bd)
- Data as of 2026-08-30T08:39:29.467469+00:00.