# SpinalHDL/SpinalHDL

Scala based HDL

Repository: https://github.com/SpinalHDL/SpinalHDL
Canonical: https://ross.abutalabs.com/products/spinalhdl
Language: Scala
License: NOASSERTION
License Family: other
Topics: scala, rtl, vhdl, verilog, fpga
Last push: 2026-08-12T07:15:05+00:00

## Health v2 (maintenance only)
Score: 85/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 97, release rhythm 62, longevity 100
- inputs: {"age_days": 4238, "days_push": 21, "days_rel": 98, "gap_med": 91, "n_releases_24m": 8}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2031, forks 388 (observed 2026-08-28T04:06:07.311059+00:00)

## What it is
SpinalHDL is an open-source Scala-based hardware description language (HDL) library for describing digital hardware at the register-transfer level (RTL). It generates standard VHDL and Verilog output compatible with existing EDA tools, while offering the expressiveness of a modern programming language with object-oriented and functional programming features.

## Use cases
- describe digital hardware using a modern Scala-based HDL instead of VHDL or Verilog
- generate VHDL and Verilog RTL code for FPGA or ASIC synthesis
- use object-oriented and functional programming to parameterize and elaborate hardware designs
- write less verbose, more powerful hardware descriptions than SystemVerilog
- verify hardware designs using Scala-based testing and simulation
- build reusable hardware component libraries with software engineering practices
- design FPGA circuits without area or performance overhead versus hand-written HDL

## When to choose
- you want a modern, expressive HDL with strong typing and OOP/FP features instead of VHDL/Verilog/SystemVerilog
- you need to generate standard VHDL or Verilog that works with your existing EDA toolchain
- you want to parameterize and generate hardware programmatically with Scala libraries
- you prefer concise hardware descriptions with one-to-one, no-black-magic RTL generation
- you want a free, industry-usable HDL without licensing costs

## When to avoid
- you need high-level synthesis (HLS) from C/C++ or similar - SpinalHDL is explicitly not an HLS tool
- your team and toolchain are firmly committed to VHDL, Verilog, or SystemVerilog with no room for a Scala-based flow
- you require an event-driven simulation paradigm - SpinalHDL is RTL-based
- your environment cannot run the JVM or Scala build tooling (SBT/Gradle)
- you need a standalone language with its own compiler rather than an embedded Scala DSL

## Facets
- artifact type: library
- maturity: active
- function: programming-language, compiler, simulation, testing
- domain: hardware, embedded-systems
- platform: jvm, cross-platform
- tags: hdl, rtl, hardware-description-language, vhdl, verilog, systemverilog, fpga, asic, scala, hardware-construction, rtl-generation, eda-tools, digital-circuit-design, hardware-verification, chisel-alternative, digital-design, eda

## Member repositories
- SpinalHDL/SpinalHDL (main) score 85

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:07.311059+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:59:31.589217+00:00, confidence not recorded.
  - readme: https://github.com/SpinalHDL/SpinalHDL (fetched 2026-08-28T04:06:07.311059+00:00, sha 32b5765702f8)
- Data as of 2026-08-30T08:39:29.467469+00:00.