# sylefeb/Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Repository: https://github.com/sylefeb/Silice
Canonical: https://ross.abutalabs.com/products/silice
Language: C++
License: NOASSERTION
License Family: other
Topics: fpga, programming, language
Last push: 2026-08-23T16:48:49+00:00

## Health v2 (maintenance only)
Score: 77/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 99, release rhythm 35, longevity 100
- inputs: {"age_days": 2522, "days_push": 10, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1430, forks 101 (observed 2026-08-28T04:04:42.272031+00:00)

## What it is
Silice is an open-source hardware description language designed to make writing FPGA hardware algorithms with pipelines and parallelism easy to learn and expressive. It includes a compiler toolchain, board support, simulation, formal verification, and many example projects such as RISC-V CPUs and a Doom GPU.

## Use cases
- write hardware algorithms for FPGAs without deep Verilog expertise
- design pipelined and parallel hardware logic
- prototype parametric hardware designs quickly
- simulate and formally verify FPGA designs
- build small RISC-V CPUs or GPU-like accelerators on FPGA

## When to choose
- you want an easier, C-like alternative to Verilog for FPGA development
- you need pipelines and parallelism as first-class language constructs
- you want a ready-to-go environment with many FPGA boards and example projects

## When to avoid
- you need an industry-standard HDL for a production ASIC flow
- your team already has deep Verilog/VHDL expertise and tooling
- you require long-term stability, as the language is under active development with occasional breaking changes

## Facets
- artifact type: cli-tool
- maturity: active
- function: programming-language, compiler, simulation
- domain: hardware, programming-languages, developer-tools
- platform: windows, cli
- tags: fpga, hardware-description-language, verilog, risc-v, pipelines, parallelism, formal-verification, programming-language, linux, macos

## Member repositories
- sylefeb/Silice (main) score 77

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:42.272031+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T08:33:00.223028+00:00, confidence not recorded.
  - readme: https://github.com/sylefeb/Silice (fetched 2026-08-28T04:04:42.272031+00:00, sha 06922b9e1261)
- Data as of 2026-08-30T08:39:29.467469+00:00.