# syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Repository: https://github.com/syntacore/scr1
Canonical: https://ross.abutalabs.com/products/scr1
Language: SystemVerilog
License: NOASSERTION
License Family: other
Topics: riscv, risc-v, rtl, verilog, rv32i, rv32e, rv32imc, rv32emc, ip, core
Last push: 2024-11-15T14:23:23+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 3403, "days_push": 656, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 999, forks 349 (observed 2026-09-03T02:15:18.344240+00:00)

## Summary
No AI-extracted summary yet.

## Member repositories
- syntacore/scr1 (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-09-03T02:15:18.344240+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Data as of 2026-08-30T08:39:29.467469+00:00.