# rust-embedded/riscv

Low level access to RISC-V processors

Repository: https://github.com/rust-embedded/riscv
Canonical: https://ross.abutalabs.com/products/rust-embedded-riscv
Language: Rust
License: Apache-2.0
License Family: permissive
Last push: 2026-08-18T10:44:35+00:00

## Health v2 (maintenance only)
Score: 77/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 98, release rhythm 38, longevity 100
- inputs: {"age_days": 3270, "days_push": 15, "days_rel": 252, "gap_med": 105, "n_releases_24m": 4}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1126, forks 200 (observed 2026-08-28T04:03:41.332880+00:00)

## What it is
A collection of Rust crates providing low-level access to RISC-V processors, including CPU register access, intrinsics, standard peripheral interfaces, startup code, interrupt handling, and semihosting support. It is maintained by the Rust Embedded working group's RISC-V team and serves as a foundation for writing bare-metal Rust programs on RISC-V microcontrollers.

## Use cases
- access risc-v cpu registers and intrinsics from rust
- write bare-metal rust firmware for risc-v microcontrollers
- handle interrupts and startup code on risc-v targets
- interface with standard risc-v peripherals like clint and plic
- use semihosting to debug risc-v programs
- build a risc-v pac crate with common traits
- parse risc-v target specifications in build scripts

## When to choose
- you are writing no_std rust code for a risc-v microcontroller
- you need low-level register and peripheral access on risc-v
- you are building a hardware abstraction layer or pac for a risc-v chip
- you want a maintained, community-backed foundation crate for risc-v embedded rust

## When to avoid
- you are targeting arm or other non-risc-v architectures
- you need a high-level hal with drivers for specific boards rather than low-level access
- you are writing hosted application code that does not touch hardware directly

## Facets
- artifact type: library
- maturity: stable
- function: embedded, developer-tools
- domain: embedded-systems, developer-tools
- platform: embedded, rust
- tags: risc-v, microcontroller, bare-metal, no-std, registers, peripherals, interrupt-handling, semihosting, startup-code, pac

## Member repositories
- rust-embedded/riscv (main) score 77

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:41.332880+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:39:13.518725+00:00, confidence not recorded.
  - readme: https://github.com/rust-embedded/riscv (fetched 2026-08-28T04:03:41.332880+00:00, sha d769beae4cd1)
  - registry_crates: https://crates.io/api/v1/crates/riscv (fetched 2026-08-29T12:43:37.510986+00:00, sha 6c59f08af130)
- Data as of 2026-08-30T08:39:29.467469+00:00.