# riscv-software-src/riscv-isa-sim

Spike, a RISC-V ISA Simulator

Repository: https://github.com/riscv-software-src/riscv-isa-sim
Canonical: https://ross.abutalabs.com/products/riscv-isa-sim
Homepage: https://riscv.atlassian.net/browse/RVG-476
Language: C
License: NOASSERTION
License Family: other
Last push: 2026-08-24T23:04:04+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 8, longevity 100
- inputs: {"age_days": 5486, "days_push": 9, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3208, forks 1097 (observed 2026-08-28T04:07:48.678539+00:00)

## What it is
Spike is the official RISC-V ISA simulator, providing a functional model of one or more RISC-V harts. It implements a broad range of RISC-V base ISAs and extensions, serving as the reference simulator for RISC-V software development.

## Use cases
- simulate RISC-V programs on x86 machines
- test RISC-V kernel and OS code before hardware is available
- run RISC-V bare-metal binaries with the proxy kernel
- validate new RISC-V ISA extension implementations
- develop and debug RISC-V toolchains

## When to choose
- you need the reference functional simulator for RISC-V ISA development
- you want to test software against the latest RISC-V extensions
- you are developing compilers, kernels, or bootloaders for RISC-V

## When to avoid
- you need cycle-accurate or performance modeling rather than functional simulation
- you need fast full-system emulation of a complete Linux environment (consider QEMU)
- you want a graphical or interactive debugging environment out of the box

## Facets
- artifact type: application
- maturity: active
- function: simulation, interpreter, developer-tools
- domain: hardware, developer-tools, operating-systems
- platform: windows, cross-platform, cli
- tags: risc-v, isa-simulator, emulator, spike, instruction-set-simulation, linux, macos

## Member repositories
- riscv-software-src/riscv-isa-sim (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:48.678539+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:44:57.875446+00:00, confidence not recorded.
  - readme: https://github.com/riscv-software-src/riscv-isa-sim (fetched 2026-08-28T04:07:48.678539+00:00, sha db52d811f0aa)
  - homepage: https://riscv.atlassian.net/browse/RVG-476 (fetched 2026-08-29T09:38:16.015188+00:00, sha 9b9e8314182f)
- Data as of 2026-08-30T08:39:29.467469+00:00.