# The-OpenROAD-Project/OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Repository: https://github.com/The-OpenROAD-Project/OpenROAD
Canonical: https://ross.abutalabs.com/products/openroad
Homepage: https://theopenroadproject.org/
Language: Verilog
License: BSD-3-Clause
License Family: permissive
Topics: opendb-database, openroad, lef, verilog, timing-analysis, def, eda, rtl, gdsii, cpp, tcl
Last push: 2026-08-26T19:24:00+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 8, longevity 100
- inputs: {"age_days": 2501, "days_push": 7, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3023, forks 994 (observed 2026-08-28T04:07:38.476717+00:00)

## What it is
OpenROAD is an open-source application implementing a unified RTL-to-GDSII flow for digital chip design, covering synthesis through floorplanning, placement, clock tree synthesis, routing, and finishing. It aims for autonomous, no-human-in-loop physical design with 24-hour turnaround from RTL to final layout.

## Use cases
- run an RTL-to-GDSII flow for digital IC design
- perform floorplanning, placement, and routing for a chip layout
- do static timing analysis on a netlist
- explore physical design implementations without commercial EDA licenses
- generate GDSII final layout from Verilog and library files
- automate no-human-in-loop chip implementation

## When to choose
- you need an open-source alternative to commercial physical design tools
- you want rapid RTL-to-GDSII turnaround for design exploration
- you are doing academic or research ASIC/IC design
- you need scripting-driven, automated place-and-route with Tcl

## When to avoid
- you need analog or mixed-signal design tools
- you require certified production sign-off flows with vendor support
- you are designing FPGAs rather than ASICs
- you need a GUI-first interactive layout editor

## Facets
- artifact type: application
- maturity: active
- function: compiler, simulation, developer-tools, cli
- domain: hardware, developer-tools
- platform: cpp
- tags: rtl-to-gdsii, physical-design, eda, place-and-route, timing-analysis, opendb, asic-design-flow, chip-design, linux, macos, tcl

## Member repositories
- The-OpenROAD-Project/OpenROAD (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:38.476717+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T07:29:55.066483+00:00, confidence not recorded.
  - readme: https://github.com/The-OpenROAD-Project/OpenROAD (fetched 2026-08-28T04:07:38.476717+00:00, sha f4fb85304d8b)
  - homepage: https://theopenroadproject.org/ (fetched 2026-08-29T09:45:01.029970+00:00, sha d30042715c6e)
- Data as of 2026-08-30T08:39:29.467469+00:00.