# lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

Repository: https://github.com/lnis-uofu/OpenFPGA
Canonical: https://ross.abutalabs.com/products/openfpga
Homepage: https://openfpga.readthedocs.io/en/master/
Language: Verilog
License: MIT
License Family: permissive
Topics: fpga, fpga-soc
Last push: 2026-09-02T18:22:27+00:00

## Health v2 (maintenance only)
Score: 68/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 100, release rhythm 8, longevity 100
- inputs: {"age_days": 3002, "days_push": 0, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1142, forks 205 (observed 2026-09-03T02:15:14.551670+00:00)

## What it is
OpenFPGA is the first open-source FPGA IP generator with silicon proofs, supporting highly customizable FPGA architectures. It provides a complete EDA flow for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification.

## Use cases
- generate FPGA IP cores from custom architecture descriptions
- produce bitstreams for a custom FPGA fabric from Verilog
- prototype and explore new FPGA architectures in research
- run full Verilog-to-bitstream EDA flow for an open-source FPGA
- verify and self-test generated FPGA designs
- build an FPGA-based SoC with a customized fabric

## When to choose
- you need to design or research custom FPGA architectures with an open toolchain
- you want silicon-proven, open-source FPGA IP generation
- you need a complete Verilog-to-bitstream flow for a bespoke FPGA
- you are exploring agile hardware prototyping for reconfigurable fabrics

## When to avoid
- you only need to program a commercial off-the-shelf FPGA like Xilinx or Intel parts
- you need a general-purpose HDL simulator rather than an FPGA generator
- your project requires vendor-proprietary tooling and support

## Facets
- artifact type: framework
- maturity: active
- function: compiler, simulation, developer-tools
- domain: hardware
- platform: cli
- tags: fpga-ip-generator, verilog, bitstream-generation, eda-tools, chip-design, silicon-proven, fpga-architecture, code-generation, eda, fpga, computer-architecture, research, linux, macos, docker

## Member repositories
- lnis-uofu/OpenFPGA (main) score 68

## Provenance
- Observed fields: from GitHub, fetched 2026-09-03T02:15:14.551670+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:36:31.562181+00:00, confidence not recorded.
  - readme: https://github.com/lnis-uofu/OpenFPGA (fetched 2026-09-03T02:15:14.551670+00:00, sha 0b6fdd429a92)
- Data as of 2026-08-30T08:39:29.467469+00:00.