# icedland/iced

Blazing fast and correct x86/x64 disassembler, assembler, decoder, encoder for Rust, .NET, Java, Python, Lua

Repository: https://github.com/icedland/iced
Canonical: https://ross.abutalabs.com/products/icedland-iced
Language: Rust
License: MIT
License Family: permissive
Topics: disassembler, assembler, x86, x64, decoder, encoder
Last push: 2026-08-17T08:45:21+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 98, release rhythm 8, longevity 100
- inputs: {"age_days": 2917, "days_push": 16, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3556, forks 273 (observed 2026-08-28T04:08:09.676564+00:00)

## What it is
iced is a fast and correct x86/x64 (16/32/64-bit) instruction decoder, disassembler, and assembler library with bindings for Rust, .NET, Java, Python, Lua, and JavaScript (WebAssembly). It supports all Intel and AMD instructions, multiple formatter syntaxes (masm, nasm, gas/AT&T, Intel/XED), and includes an encoder for re-encoding instructions at arbitrary addresses.

## Use cases
- disassemble x86-64 machine code
- assemble instructions programmatically
- decode binary machine code into instructions
- re-encode decoded instructions at a different address
- get instruction info like read/written registers and rflags
- format disassembly in nasm, masm, gas, or Intel syntax
- build a binary analysis or reverse engineering tool

## When to choose
- you need a high-performance, thoroughly tested x86/x64 disassembler or assembler
- you need bindings for Rust, .NET, Java, Python, Lua, or JavaScript
- you need instruction metadata such as CPUID feature flags, register/memory access, and control flow info
- correctness matters and you want a library fuzz-tested against xed, gas, objdump, masm, nasm, and ndisasm

## When to avoid
- you need to disassemble non-x86 architectures like ARM, RISC-V, or MIPS
- you need a full decompiler or static analysis framework rather than a decoder/assembler
- you need a GUI disassembler like Ghidra or IDA

## Facets
- artifact type: library
- maturity: active
- function: parser, compiler, reverse-engineering, developer-tools
- domain: reverse-engineering, developer-tools, compilers
- platform: rust, python, jvm, dotnet, wasm, cross-platform
- tags: x86, x64, disassembler, assembler, decoder, encoder, instruction-decoding, multi-language-bindings

## Member repositories
- icedland/iced (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:09.676564+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:34:16.307704+00:00, confidence not recorded.
  - readme: https://github.com/icedland/iced (fetched 2026-08-28T04:08:09.676564+00:00, sha 07384fa50b81)
- Data as of 2026-08-30T08:39:29.467469+00:00.