# nvdla/hw

RTL, Cmodel, and testbench for NVDLA

Repository: https://github.com/nvdla/hw
Canonical: https://ross.abutalabs.com/products/hw
Language: Verilog
License: NOASSERTION
License Family: other
Last push: 2022-03-02T14:10:39+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 3264, "days_push": 1645, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2141, forks 654 (observed 2026-08-28T04:06:18.385598+00:00)

## What it is
The hardware release of NVIDIA's open-source Deep Learning Accelerator (NVDLA), containing Verilog RTL, a C-model, testbenches, and synthesis scripts for a configurable deep learning inference accelerator. It provides a modular, scalable architecture intended for integration into SoC designs.

## Use cases
- integrate a deep learning inference accelerator into a custom SoC
- simulate and validate NVDLA RTL with trace-player testbenches
- synthesize the NVDLA design for FPGA or ASIC targets
- study open-source neural accelerator microarchitecture
- estimate accelerator performance with the provided perf model
- run sanity simulations of the full-precision NVDLA configuration

## When to choose
- you need an open, licensable DLA hardware design to integrate into your chip or FPGA project
- you want to study or extend an industrial-grade deep learning accelerator RTL
- you need a C-model reference for hardware/software co-verification

## When to avoid
- you need a software-only inference library or GPU runtime
- you expect active feature development - the nvdlav1 branch is a sustaining release with bug fixes only
- you need a turnkey product rather than RTL IP requiring integration effort

## Facets
- artifact type: library
- maturity: maintenance
- function: machine-learning, deep-learning, simulation, embedded
- domain: deep-learning, hardware, embedded-systems, machine-learning
- platform: embedded
- tags: rtl, verilog, hardware-accelerator, nvdla, inference-accelerator, c-model, testbench, synthesis

## Member repositories
- nvdla/hw (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:18.385598+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:51:22.355570+00:00, confidence not recorded.
  - readme: https://github.com/nvdla/hw (fetched 2026-08-28T04:06:18.385598+00:00, sha 301a0c258753)
- Data as of 2026-08-30T08:39:29.467469+00:00.