# janestreet/hardcaml

Hardcaml is an OCaml library for designing hardware.

Repository: https://github.com/janestreet/hardcaml
Canonical: https://ross.abutalabs.com/products/hardcaml
Language: OCaml
License: MIT
License Family: permissive
Last push: 2026-07-10T16:45:36+00:00

## Health v2 (maintenance only)
Score: 64/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 91, release rhythm 8, longevity 100
- inputs: {"age_days": 3024, "days_push": 54, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1118, forks 64 (observed 2026-08-28T04:03:39.109551+00:00)

## What it is
Hardcaml is an OCaml library for designing and testing hardware circuits, letting users express hardware designs using OCaml's type system and metaprogramming features. It includes a simulation backend and can compile designs to hierarchical Verilog or VHDL for FPGA synthesis.

## Use cases
- design hardware circuits in OCaml instead of Verilog or VHDL
- simulate digital hardware designs with waveform visualization
- generate parameterized RTL pipelines using higher-order functions and functors
- compile hardware designs to Verilog or VHDL for FPGA synthesis
- write custom backends or circuit analysis tools
- avoid type-confusion bugs in hardware signal wiring

## When to choose
- you want to use a strongly typed functional language for hardware design
- you need to generate large unrolled or pipelined hardware designs programmatically
- you want to simulate and validate hardware entirely within OCaml
- you value code reuse and parametrization across hardware projects

## When to avoid
- you need an industry-standard HDL workflow with existing Verilog/VHDL tooling and IP
- your team has no OCaml experience
- you need analog or mixed-signal design capabilities
- you require vendor-specific synthesis features not covered by RTL export

## Facets
- artifact type: library
- maturity: active
- function: simulation, compiler, testing, developer-tools
- domain: hardware, embedded-systems, programming-languages, developer-tools
- platform: windows, cross-platform
- tags: hardware-description-language, rtl, fpga, verilog, vhdl, ocaml, circuit-design, digital-design, linux, macos

## Member repositories
- janestreet/hardcaml (main) score 64

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:39.109551+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:41:48.477149+00:00, confidence not recorded.
  - readme: https://github.com/janestreet/hardcaml (fetched 2026-08-28T04:03:39.109551+00:00, sha a41ded7e0286)
- Data as of 2026-08-30T08:39:29.467469+00:00.