# ucb-bar/gemmini

Berkeley's Spatial Array Generator

Repository: https://github.com/ucb-bar/gemmini
Canonical: https://ross.abutalabs.com/products/gemmini
Language: Scala
License: NOASSERTION
License Family: other
Topics: asic, dnn, accelerator
Last push: 2026-06-30T07:43:14+00:00

## Health v2 (maintenance only)
Score: 63/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 90, release rhythm 8, longevity 100
- inputs: {"age_days": 2864, "days_push": 64, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1436, forks 286 (observed 2026-08-28T04:04:43.592559+00:00)

## What it is
Gemmini is Berkeley's open-source generator for parameterizable systolic-array DNN hardware accelerators, written in Chisel (Scala) and integrated with the Chipyard SoC design ecosystem. It provides a full-system, full-stack platform for exploring and evaluating how hardware and software co-design choices affect deep neural network performance, including simulators and software toolchains.

## Use cases
- generate a custom systolic array DNN accelerator for RISC-V SoCs
- evaluate DNN accelerator performance in cycle-accurate simulation
- explore hardware-software co-design tradeoffs for neural network accelerators
- run ResNet50 and other DNN models on a simulated custom accelerator
- prototype an ASIC or FPGA neural network accelerator
- study how memory hierarchies and software stacks affect DNN accelerator performance

## When to choose
- you are a computer architect researching DNN accelerator designs
- you need a parameterizable systolic array generator integrated with RISC-V SoCs via Chipyard
- you want full-system simulation of custom accelerators with real DNN workloads
- you are building an academic or research prototype of a matrix-multiplication accelerator

## When to avoid
- you need a production-ready commercial accelerator or driver stack
- you want to accelerate DNNs on existing GPUs or CPUs without hardware design work
- you are unfamiliar with Chisel, RISC-V, and hardware simulation flows
- you need a quick plug-and-play inference solution

## Facets
- artifact type: framework
- maturity: active
- function: simulation, machine-learning, deep-learning, compiler, developer-tools
- domain: hardware, machine-learning, deep-learning, simulation
- platform: python, cpp, jvm
- tags: hardware-accelerator, chisel, risc-v, asic, dnn, systolic-array, chipyard, fpga, hardware-design, research, linux

## Member repositories
- ucb-bar/gemmini (main) score 63

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:43.592559+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:36:49.231747+00:00, confidence not recorded.
  - readme: https://github.com/ucb-bar/gemmini (fetched 2026-08-28T04:04:43.592559+00:00, sha 39b0a8479dd5)
- Data as of 2026-08-30T08:39:29.467469+00:00.