# riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

Repository: https://github.com/riscv-mcu/e203_hbirdv2
Canonical: https://ross.abutalabs.com/products/e203_hbirdv2
Homepage: https://doc.nucleisys.com/hbirdv2
Language: Verilog
License: Apache-2.0
License Family: permissive
Topics: risc-v, riscv, fpga, hummingbird, nuclei, soc, e203, china, verilog, low-power, cpu, core
Last push: 2025-08-06T02:51:06+00:00

## Health v2 (maintenance only)
Score: 48/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 35, release rhythm 35, longevity 100
- inputs: {"age_days": 2226, "days_push": 392, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1903, forks 428 (observed 2026-08-28T04:05:51.771400+00:00)

## What it is
Hummingbirdv2 E203 is an open-source ultra-low power 32-bit RISC-V processor core and SoC written in Verilog, developed by Nuclei System Technology. It includes a configurable RV32IMAC core with the NICE co-unit extension, an SoC with APB peripherals (GPIO, I2C, UART, SPI, PWM), FPGA board support, and simulation flows.

## Use cases
- learn RISC-V processor architecture from readable Verilog source
- build a low-power RISC-V MCU SoC on an FPGA
- add custom hardware accelerators via the NICE co-unit interface
- run embedded firmware on an open-source RISC-V SoC in simulation
- prototype custom RISC-V cores for academic and non-commercial projects
- study SoC peripheral implementations like UART, SPI, and I2C in Verilog

## When to choose
- you need an open-source, well-documented RISC-V core and SoC in Verilog for FPGA or ASIC study
- you want to extend a RISC-V core with custom instructions using NICE
- you are teaching or learning embedded RISC-V design with simulation and FPGA flows

## When to avoid
- you need a high-performance, out-of-order, or 64-bit application-class core
- you require commercial licensing or production-grade silicon-proven IP support
- you prefer SystemVerilog/UVM verification environments or non-RISC-V ISAs

## Facets
- artifact type: library
- maturity: stable
- function: embedded, simulation, developer-tools
- domain: embedded-systems, hardware, developer-tools
- platform: windows
- tags: risc-v, verilog, soc, fpga, low-power, cpu-core, open-source-hardware, nuclei, hummingbird, e203, linux

## Member repositories
- riscv-mcu/e203_hbirdv2 (main) score 48

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:51.771400+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:11:53.514832+00:00, confidence not recorded.
  - readme: https://github.com/riscv-mcu/e203_hbirdv2 (fetched 2026-08-28T04:05:51.771400+00:00, sha 265fe663d130)
  - homepage: https://doc.nucleisys.com/hbirdv2 (fetched 2026-08-29T10:51:10.515239+00:00, sha 10cb77cb0e0e)
  - site_page: https://doc.nucleisys.com/hbirdv2/changelog.html (fetched 2026-08-29T10:51:10.524225+00:00, sha 819b78756d78)
  - site_page: https://doc.nucleisys.com/hbirdv2/core/core.html (fetched 2026-08-29T10:51:10.526090+00:00, sha 91c115858f52)
  - site_page: https://doc.nucleisys.com/hbirdv2/quick_start/ide.html (fetched 2026-08-29T10:51:10.528106+00:00, sha 2ddde2feb710)
  - site_page: https://doc.nucleisys.com/hbirdv2/quick_start/ide_latest.html (fetched 2026-08-29T10:51:10.529840+00:00, sha b2f697290f83)
- Data as of 2026-08-30T08:39:29.467469+00:00.