# Digital-EDA/Digital-IDE

All in one vscode plugin for HDL development

Repository: https://github.com/Digital-EDA/Digital-IDE
Canonical: https://ross.abutalabs.com/products/digital-ide
Language: VHDL
License: MIT
License Family: permissive
Last push: 2026-03-05T05:33:00+00:00

## Health v2 (maintenance only)
Score: 65/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 70, release rhythm 41, longevity 94
- inputs: {"age_days": 1321, "days_push": 181, "days_rel": 181, "gap_med": null, "n_releases_24m": 1}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1158, forks 67 (observed 2026-08-28T04:03:48.496072+00:00)

## What it is
Digital IDE is an all-in-one VSCode extension for hardware description language development, supporting Verilog, VHDL, and SystemVerilog. It provides a Rust-based language server, syntax highlighting, documentation generation, VCD waveform rendering, netlist visualization, and integration with tools like Vivado, ModelSim, and Verilator.

## Use cases
- write and edit Verilog or VHDL in VSCode with autocomplete and linting
- view VCD simulation waveforms inside the editor
- generate documentation from HDL source comments
- run simulations with Icarus Verilog, Verilator, or ModelSim
- render netlist diagrams from HDL designs
- get syntax highlighting for XDC and TCL constraint scripts

## When to choose
- you develop FPGA or ASIC designs in Verilog, VHDL, or SystemVerilog and use VSCode
- you want an integrated HDL IDE with LSP, linting, and waveform viewing in one plugin
- you need documentation and netlist visualization for HDL projects

## When to avoid
- you use a commercial IDE like Vivado or Quartus exclusively and prefer their built-in editors
- you need full SystemVerilog verification features like UVM class support
- you don't work with hardware description languages

## Facets
- artifact type: plugin
- maturity: active
- function: editor, parser, documentation, developer-tools, simulation
- domain: developer-tools, hardware, embedded-systems
- platform: editor-plugin, cross-platform
- tags: hdl, verilog, vhdl, systemverilog, fpga, vscode-extension, lsp, waveform-viewer, eda

## Member repositories
- Digital-EDA/Digital-IDE (main) score 65

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:48.496072+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:31:55.947325+00:00, confidence not recorded.
  - readme: https://github.com/Digital-EDA/Digital-IDE (fetched 2026-08-28T04:03:48.496072+00:00, sha b29cbdfca4cd)
- Data as of 2026-08-30T08:39:29.467469+00:00.