# B-Lang-org/bsc

Bluespec Compiler (BSC)

Repository: https://github.com/B-Lang-org/bsc
Canonical: https://ross.abutalabs.com/products/bsc
Language: Haskell
License: NOASSERTION
License Family: other
Last push: 2026-08-24T05:34:07+00:00

## Health v2 (maintenance only)
Score: 82/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 49, longevity 100
- inputs: {"age_days": 2406, "days_push": 9, "days_rel": 124, "gap_med": 196, "n_releases_24m": 4}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1141, forks 183 (observed 2026-08-28T04:03:44.567247+00:00)

## What it is
The Bluespec Compiler (BSC) is a compiler, simulator, and toolchain for the Bluespec Hardware Description Language, supporting both Bluespec SystemVerilog and Bluespec Haskell syntax. It emits standard Verilog for synthesis and includes the Bluesim simulator, a standard library, and TCL scripting support.

## Use cases
- compile Bluespec HDL designs to Verilog
- simulate digital hardware designs before synthesis
- write high-level hardware descriptions with guarded atomic actions
- develop CPU cores like RISC-V processors in a high-level HDL
- verify hardware designs with a strong type system before synthesis
- script hardware build flows with TCL

## When to choose
- you want a high-level, type-safe hardware description language instead of raw Verilog
- you need modular hardware design where the compiler derives schedulers from invariants
- you need Verilog output compatible with any synthesis toolchain
- you want an integrated simulator for your HDL designs

## When to avoid
- you only need to write low-level RTL directly in Verilog or VHDL
- your team has no appetite for learning a new HDL
- you need vendor-specific synthesis features not expressible in generated Verilog

## Facets
- artifact type: cli-tool
- maturity: active
- function: compiler, programming-language, simulation, developer-tools
- domain: hardware, embedded-systems, programming-languages, compilers
- platform: cli
- tags: hardware-description-language, bluespec, verilog-generation, fpga, bluesim, systemverilog, linux, macos

## Member repositories
- B-Lang-org/bsc (main) score 82

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:44.567247+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T08:33:33.777728+00:00, confidence not recorded.
  - readme: https://github.com/B-Lang-org/bsc (fetched 2026-08-28T04:03:44.567247+00:00, sha f18cf2593826)
- Data as of 2026-08-30T08:39:29.467469+00:00.